Aging Analysis

Infinisim’s Aging Analysis assesses timing degradation of full-clock domains. Customers use Infinisim’s Aging Analysis to predict the degradation and adapt the clock design accordingly for improved reliability.

At lower process nodes, secondary physical effects like Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) have become one of the most important reliability issues for high-performance designs. These secondary effects are becoming dominant aging inducing mechanisms and have a significant impact upon clock performance degradation over time.

Infinisim’s Aging Analysis performs SPICE accurate, full clock domain simulations. The analysis flow consists of SPICE accurate Fresh, Stress and Aging simulations using parked signal conditions.

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Application and Capabilities

Customers use Aging Analysis to assess timing degradation of full-clock domain

Performance

Aging results are computed for multi-million gate clock domains, at SPICE accuracy, in overnight runs.

Reporting

Reports provide comprehensive comparative analysis of Fresh vs. Aged timing degradation


Aging Flow

The aging analysis flow consists of Fresh, Stress and Aging simulations. During the Fresh simulation, the activity of all gates in a clock domain is simulated. The Stress simulation takes the transistor activity computed during Fresh simulation and computes physical degradation for each transistor. The Aging simulation takes the degraded device model computed during the Stress simulation and simulates the effect of degraded model on the clock signal propagation.

Our Solutions

SoC Clock Analysis

Our leading edge clock analysis solution helps customers accurately verify timing, detect failures, and optimize performance of the clock.

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Clock Jitter Analysis

Our specialized jitter engine helps customers compute power supply induced jitter of clock domains at SPICE accuracy. 

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Comprehensive Solution for

 

Full Chip Clock Analysis