Infinisim’s ClockEdge is a high-capacity, high-performance, SPICE accurate, end-to-end integrated clock analysis solution. ClockEdge is used as a sign-off solution for full-chip, multiple topologies, high-speed clocks. Our customers are leading edge fabless semiconductor companies and foundries that are designing high performance chips at advanced process nodes.
Customers use ClockEdge to augment STA for SPICE accurate, comprehensive timing analysis that enables:
- Timing optimization during design iterations
- BTO/MTO sign-off verification
- Post fab investigation into performance degradation and potential improvements for next revision.
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Application and Capabilities
Customers use ClockEdge to accurately analyze top-level, block-level and hard-macro level clocks.
ClockEdge is the only solution which practically analyzes top-level SOC clock with multi-million gates at SPICE level accuracy. Using a scalable distributed model, SPICE accurate results for clock domains containing 4+ million gates can be generated overnight.
ClockEdge generates multiple reports including timing, process variation, power and current analysis and custom reports. Timing reports include:
- Slew rates at gate and interconnect nets
- Gate delays in the clock path
- Skew between launch and capture flops
- Duty cycle at gate and interconnect nets
- Peak-to-Peak voltage swing
ClockEdge starts with generating a transistor-level netlist from Verilog gate-level clock domain tracing. Clock paths are then sensitized to ensure clock signal propagation through complex gates. High-speed, high-capacity, SPICE accurate circuit simulation is performed for multiple PVTs and Monte Carlo analysis.
ClockEdge enables numerous analysis capabilities:
- Analysis of multiple PVT corners per clock, each clock containing millions of gates
- Node-based analysis at inputs and outputs of each gate
- Intra-PVT sensitivity analysis
- ECO validation
- Clock distribution topology analysis
OCV analysis in nanometer technologies
Nanometer designs have significant OCV impacting yield. ClockEdge uses best-in-class speed, accuracy and capacity Monte-Carlo based OCV analysis. OCV analysis is used both during design iterations for reducing guard-banding and in post design phase to estimate yield.
CTS flow integration
- Timing information generated by ClockEdge can be integrated into CTS flow for optimizing and iterative design improvements.
- ClockEdge flow is designed to augment the STA flow.
Clock Jitter Analysis
Our specialized jitter engine helps customers compute power supply induced jitter of clock domains at SPICE accuracy.
Clock Aging Analysis
Our Clock Aging Analysis helps customers estimate the operational lifetime of power-sensitive clocks using SPICE accurate simulation.
Comprehensive Solution for
Full Chip Clock Analysis