-  Products
-  White Papers
-  Evaluation Request
ClockEdge™: SPICE Accurate Clock Analysis
ClockEdge™ is a full-chip clock analysis tool for sign-off. ClockEdge™ provides SPICE accurate skew, slew, duty cycle and other timing information that can be used to improve performance and yield.

ClockEdge™ seamlessly bridges the gap between gate-level design and transistor-level verification. ClockEdge™ is designed specifically to take a gate-level design and analyze the clock at full SPICE accuracy with minimal user intervention. Clock networks are traced using existing gate-level circuit used in traditional STA flow. The gate-level clock circuit is automatically converted into a transistor-level netlist with all parasitics, and simulated at full SPICE accuracy.

ClockEdge™ Application & Capabilities

Customers use ClockEdge™ to accurately analyze top-level, block-level and hard-macro level clocks.

  • Analyze advance clock topologies
    • High performance designs use advance topologies to minimize skew and slew rates. STA based timing methodologies are limited to standard tree-based clock designs. ClockEdge™ analyzes advance clock designs with meshes and grids along with trees.
  • SPICE accurate full-chip clock timing and power analysis
    • Accurate timing analysis is vital for reducing guard-banding in high speed designs. Power analysis is essential in low-power designs. ClockEdge™ provides both timing and power analysis, i.e., peak, average, rms, leakage power, using dynamic simulation. ClockEdge™ can also generate currents through signal wire for EM analysis.
  • OCV analysis in nanometer technologies
    • Nanometer designs have significant OCV impacting yield. ClockEdge™ uses best-in-class speed, accuracy and capacity Monte-Carlo based OCV analysis. OCV analysis is used both during design iterations for reducing guard-banding and in post design phase to estimate yield.
  • Augments existing STA based clock synthesis flow
    • ClockEdge™ flow is designed to complement the STA flow. STA based flow can be used for initial design iterations and ClockEdge™ flow is used to verify and improve STA results. ClockEdge™ provides more than just timing information, it can also be used as an accurate, high speed and high capacity simulator, e.g., determine duty-cycle and jitter in PLLs due clock networks.
  • Integration into CTS flow
    • Timing information generated by ClockEdge™ can be integrated into CTS flow for optimizing and iterative design improvements.