Jitter Analysis

Infinisim JitterEdge is a specialized jitter analytics solution, designed to compute power supply induced jitter of clock domains containing millions of gates at SPICE accuracy. It computes both period and cycle-to-cycle jitter at all clock nets, for all transitions using large milli-second power-supply noise profiles. Customers use Infinisim jitter analysis during physical design iterations and before final tape-out to ensure timing closure.

Power supply voltage noise due to transient load currents results in timing jitter in clock signals. The timing variation due to jitter becomes significant in circuits running at high frequencies at low supply voltages. Computing accurate jitter is a requirement for any high-performance designs and is essential for realistic timing margins. Underestimating jitter can lead to catastrophic timing failure and overly pessimistic clock jitter results in excessive guard-banding and lower design performance.

Infinisim’s jitter analysis for high performance clocks yields sub-pico second resolution jitter at SPICE accuracy. Maintaining full SPICE accuracy provides the confidence in the jitter value. Analyzing full clock domains using long power supply noise, substantially increases the coverage of finding worst-case jitter.

Application and Capabilities

Customers use JitterEdge to compute power supply induced Jitter


Jitter results are computed for multi-million gate clock domains, at SPICE accuracy, in overnight runs. 


Reporting includes period and cycle-to-cycle jitter at each individual net, for all clock periods, using multiple millisecond-long power supply noise profiles. 

Jitter Flow

Using ClockEdge based tracing and sensitization, the Jitter analytics solution adds large millisecond power supply noise waveforms to calculate clock timing jitter at sub-pico second resolution. 

Our Solutions

SoC Clock Analysis

Our leading edge clock analysis solution helps customers accurately verify timing, detect failures, and optimize performance of the clock.

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Clock Aging Analysis

Our Clock Aging Analysis helps customers estimate the operational lifetime of power-sensitive clocks using SPICE accurate simulation.

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Comprehensive Solution for


Full Chip Clock Analysis